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document number: MC33663 rev. 1.0, 7/2012 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2012. all rights reserved. lin 2.1 / saej2602-2 dual lin physical layer the local interconnect network (l in) is a serial communication protocol designed to support automoti ve networks in conjunction with controller area network (can). as the lowest level of a hierarchical network, lin enables cost-effecti ve communication with sensors and actuators when all the featur es of can are not required. the 33663 product line integrates two physical layer lin bus dedicated to automotive lin sub-bus applications. the MC33663lef and MC33663sef devices offer normal baud rate (20 kbps) and the MC33663jef slow baud rate (10 kbps). both devices integrate fast baud rate (above 100 kbps) for test and programming modes . they present excellent electromagnetic compatibility (emc) and radiated emission performance, electrostati c discharge (esd) robustness and safe behavior, in the event of lin bus short-to-ground or lin bus leakage during low-power mode. features ? operational from v sup 7.0 to 18 v dc, functional up to 27 v dc, and handles 40 v during load dump ? compatible with lin protocol specification 2.1, and saej2602-2 ? very high immunity against electromagnetic interference ? low standby current in sleep mode ? over-temperature protection ? permanent dominant state detection ? fast baud rate mode selection reported by rxd ? active bus waveshaping offering excellent radiated emission performance ?sustains 15.0 kv esd iec6100-4-2 on lin bus and vsup pins ? 5.0 and 3.3 v compatible digital inputs withou t any external components required figure 1. 33663 simplified application diagram dual lin transceiver ef suffix (pb-free) 98asb42565b 14-pin soicn 33663 ordering information device (add an r2 suffix for tape and reel orders) temperature range (t a ) package MC33663alef - 40 to 125c 14 soicn MC33663ajef MC33663asef vsup en1 rxd1 txd1 en2 rxd2 txd2 gnd wake1 wake2 inh1 inh2 lin1 lin2 vdd 12 v 5.0 or 3.3 v 33663 mcu regulator v bat lin interface 1 lin interface 2 1.0 k 1.0 k
analog integrated circuit device data ? 2 freescale semiconductor 33663 device variations device variations table 1. device variations freescale part no. ( add an r2 suffix for tape and reel orders) maximum baud rate temperature range (t a ) package MC33663alef 20 kbps - 40 to 125 c 14 soicn MC33663asef 20 kbps with restricted limits for transmitter and receiver symmetry MC33663ajef 10 kbps
analog integrated circuit device data ? freescale semiconductor 3 33663 internal block diagram internal block diagram figure 2. 33663 simplifi ed internal block diagram wake1 txd1 rxd1 en1 200 k ? x 1 35a en_rxd control unit inh1 lin1 vsup en_sleep rxd_int lin_en txd_int inh_on slope control receiver ? 725 k 30 k ? wake2 txd2 rxd2 en2 200 k ? x 1 35a en_rxd control unit inh2 lin2 gnd en_sleep rxd_int lin_en txd_int inh_on slope control receiver ? 725 k 30 k ? ( lin module 2 ) ( lin module 1)
analog integrated circuit device data ? 4 freescale semiconductor 33663 pin connections pin connections figure 3. 33663 14-soic pin connections table 2. 33663 pin definitions pin pin name formal name definition 1 wake1 wake input this pin is a high-voltage input used to wake-up the lin1 from sleep mode. 2 txd1 data input this pin is the transmitter input of the lin1 interface which controls the state of the bus output. 3 lin1 lin bus this bidirectional pin represents the lin1 single-wire bus transmitter and receiver. 4 lin2 lin bus this bidirectional pin represents the lin2 single-wire bus transmitter and receiver. 5 inh2 inhibit output this pin can have two main functions: c ontrolling an external switchable voltage regulator having an inhibit input, or driving an external bus resistor connected to lin2 in the master node application. 6 rxd2 data output this pin is the receiver output of the lin2 interface, which reports the state of the bus voltage to the mcu interface. 7 en2 enable control this pin controls the operation mode of the lin2 interface. 8 wake2 wake input this pin is a high-voltage input used to wake-up the lin2 device from sleep mode. 9 gnd ground this pin is the device ground pin. 10 txd2 data input this pin is the transmitter input of the lin2 in terface, which controls the state of the bus output. 11 vsup power supply this pin is device battery level power supply. 12 inh1 inhibit output this pin can have two main functions: c ontrolling an external switchable voltage regulator having an inhibit input, or driving an external bus resistor connected to lin1 in the master node application. 13 rxd1 data output this pin is the receiver output of the lin1 interface, which reports the state of the bus voltage to the mcu interface. 14 en1 enable control this pin controls the operation mode of the lin1 interface. 11 12 13 14 txd1 lin2 en1 rxd1 inh1 lin1 inh2 rxd2 en2 gnd txd2 vsup 9 10 1 2 3 4 5 6 7 8 wake1 wake2
analog integrated circuit device data ? freescale semiconductor 5 33663 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings power supply voltage (vsup) normal operation (dc) transient input voltage with external component (according to iso7637-2 & iso7637-3 & ?hardware requirements for lin, can, and flexray interfaces in automotive applications? specific ation rev. 1.1/december 2nd, 2009) (see table 4 and figure 4 ) - pulse 1 (test up to the limit for damage - class a (1) ) - pulse 2a (test up to the limit for damage - class a (1) ) - pulse 3a (test up to the limit for damage - class a (1) ) - pulse 3b (test up to the limit for damage - class a (1) ) - pulse 5b (class a) (1) v sup(ss) v sup(s1) v sup(s2a) v sup(s3a) v sup(s3b) v sup(s5b) -0.3 to 27 -100 +75 -150 +100 -0.3 to 40 v logic voltage (rxd 1,2 , txd 1,2 , en 1,2 pins) v log - 0.3 to 5.5 v wake (v wake1, v wake2 ) normal operation with in series 2*18 k ? resistor (dc) transient input voltage with external component (according to iso7637-2 & iso7637-3 & ?hardware requirements for lin, can and flexray interfaces in automotive applications? specific ation rev1.1 / december 2nd, 2009) (see table 4 and figure 5 ) - pulse 1 (test up to the limit for damage - class d (2) ) - pulse 2a (test up to the limit for damage - class d (2) ) - pulse 3a (test up to the limit for damage - class d (2) ) - pulse 3b (test up to the limit for damage - class d (2) ) v wake(ss) v wake(s1) v wake(s2a) v wake(s3a) v wake(s3b) -27 to 40 -100 +75 -150 +100 v lin bus voltage (v lin1 , v lin2 ) normal operation (dc) transient (coupled through 1.0 nf capacitor) (according to iso7637-2 & iso7637-3) (see table 4 and figure 6 ) - pulse 1 (test up to the limit for damage - class d (2) ) - pulse 2a (test up to the limit for damage - class d (2) ) - pulse 3a (test up to the limit for damage - class d (2) ) - pulse 3b (test up to the limit for damage - class d (2) ) v lin(ss) v lin(s1) v lin(s2a) v lin(s3a) v lin(s3b) -27 to 40 -100 +75 -150 +100 v notes 1. class a: all functions of a devic e/system perform as designed during and after exposure to disturbance. 2. class d: at least one function of the transceiver stops worki ng properly during the test and will return into proper operatio n automatically when the exposure to the disturbance has ended. no physical damage of the ic occurs.
analog integrated circuit device data ? 6 freescale semiconductor 33663 electrical characteristics maximum ratings electrical ratings inh voltage / current (v inh1 , v inh2 ) dc voltage transient (coupled through 1.0 nf capacitor, according to iso7637-2 & iso7637-3 & ?hardware requirements for lin, can and flexray interfaces in automotive applications? specific ation rev1.1 / december 2nd, 2009) (see table 4 and figure 7 ) - pulse 1 (test up to the limit for damage - class d (3) ) - pulse 2a (test up to the limit for damage - class d (3) ) - pulse 3a (test up to the limit for damage - class d (3) ) - pulse 3b (test up to the limit for damage - class d (3) ) v inh v inh(s1) v inh(s2a) v inh(s3a) v inh(s3b) - 0.3 to v sup + 0.3 -100 +75 -150 +100 v notes 3. class d: at least one function of the transceiver stops worki ng properly during the test and will return into proper operatio n automatically when the exposure to the disturbance has ended. no physical damage of the ic occurs. table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data ? freescale semiconductor 7 33663 electrical characteristics maximum ratings electrical ratings esd capability aecq100 human body model - jesd22/a114 (c zap = 100 pf, r zap = 1500 ? ) lin1, lin2 pins versus gnd wake1, wake2 pins versus gnd inh1, inh2 pins versus gnd all other pins charge device model - jesd22/c101 (c zap = 4.0 pf ?? corner pins (pins 1, 7, 8 and 14) all other pins (pins 2-6, 9-13) machine model - jesd22/a115 (c zap = 220 pf, r zap = 0 ? ) all pins according to ?hardware requirements for lin, can and flexray interfaces in automotive applications? specific ation rev1.1 / december 2nd, 2009 (c zap = 150 pf, r zap = 330 ? ) contact discharge, unpowered lin1, lin2 pins without capacitor lin1, lin2 pins with 220 pf capacitor vsup (10 f to ground) wake1, wake2 (2*18 k ? serial resistor) lin1, lin2 pins with 220 pf capacitor and indirect esd coupling (according to iso10605 - annex f) according to iso10605 - rev 2008 test specification (2.0 k ? / 150 pf) - unpowered - contact discharge lin1, lin2 pins without capacitor lin1, lin2 pins with 220 pf capacitor vsup (10 f to ground) wake1, wake2 (2*18 k ? serial resistor) (2.0 k ? / 330 pf) - powered - contact discharge lin1, lin2 pins without capacitor lin1, lin2 pins with 220 pf capacitor vsup (10 f to ground) wake1, wake2 (2*18 k ? serial resistor) v esd1-1 v esd1-2 v esd1-3 v esd1-4 v esd2-1 v esd2-2 v esd3-1 v esd4-1 v esd4-2 v esd4-3 v esd4-4 v esd4-5 v esd5-1 v esd5-2 v esd5-3 v esd5-4 v esd6-1 v esd6-2 v esd6-3 v esd6-4 10.0 k 8.0 k 8.0 k 4.0 k 750 750 200 15 k 15 k 25 k 20 k 15 k 25 k 25 k 25 k 25 k 8 k 8 k 25 k 25 k v table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data ? 8 freescale semiconductor 33663 electrical characteristics maximum ratings figure 4. test circuit for transient test pulses (v sup ) thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 ? c storage temperature t stg - 40 to 150 ? c thermal resistance , junction to ambient r ? ja 150 c/w peak package reflow temperature during reflow (4) , (5) t pprt note 5 ? c thermal shutdown temperature t shut 150 to 200 c thermal shutdown hysteresis temperature t hyst 20 c notes 4. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersi on soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.frees cale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i .e. mc33xxxd enter 33xxx), and review parametrics. table 4. limits / maximum test volt age for transient immunity tests test pulse v s [v] pulse repetition frequency [hz] (1/t 1 ) test duration [min] r i [ ? ] remarks 1 -100 2 1 for function test 10 for damage test 10 t 2 = 0s 2a +75 2 2 3a -150 10 50 3b +100 10 50 table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit vsup transient pulse generator (note) note waveform per iso 7637-2. test pulses 1, 2a, 3a, 3b gnd dut dut gnd d1 10 f
analog integrated circuit device data ? freescale semiconductor 9 33663 electrical characteristics maximum ratings figure 5. test circuit for transient test pulses (wake1,wake2) figure 6. test circuit for tr ansient test pulses (lin1,lin2) figure 7. test circuit for tr ansient test pulses (inh1,inh2) wake transient pulse generator 1.0 nf (note) 18 k note waveform per iso 7637-2. test pulses 1, 2a, 3a, 3b. gnd dut dut gnd 18 k lin transient pulse generator 1.0 nf (note) note waveform per iso 7637-2. test pulses 1, 2a, 3a, 3b gnd dut dut gnd inh transient pulse generator 1.0 nf (note) note waveform per iso 7637-2. test pulses 1, 2a, 3a, 3b. gnd dut dut gnd
analog integrated circuit device data ? 10 freescale semiconductor 33663 electrical characteristics static electrical characteristics static electrical characteristics table 5. static electric al characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit vsup pin (device power supply) nominal operating voltage v sup 7.0 13.5 18.0 v functional operating voltage (6) v supop 6.7 ? 27 v load dump v supld ? ? 40 v power-on reset (por) threshold v sup ramp down and inh1, inh2 goes high to low v por 3.5 ? 5.3 v power-on reset (por) hysteresis v porhyst ? 270 ? mv v sup under-voltage threshold (positive and negative) transmission disabled and lin1 ,lin2 bus goes in recessive v uvl , v uvh 5.8 ? 6.7 v v sup under-voltage hysteresis (v uvl - v uvh ) v uvhyst ? 130 ? mv supply current lin1 and lin2 in sleep mode v sup ? 13.5 v, recessive state 13.5 v < v sup < 27 v v sup ? 13.5 v, shorted to gnd i s1 i s2 i s3 ? ? ? 12.0 ? 48 22 36 140 ? a supply current lin1 normal mode - lin2 sleep mode (and vice versa) bus 1 recessive, bus 2 sleep, excluding inh1,inh2 or (bus 2 recessive, bus 1 sleep, excluding inh1,inh2) bus 1 dominant, bus 2 sleep, excluding inh1,inh2 or (bus 2 dominant, bus 1 sleep, excluding inh1,inh2) i s_n_rec1,2 i s_n_dom1,2 ? ? 4.0 6.0 5.0 8.0 ma supply current when lin1 and lin2 are in normal or slow or fast mode bus 1 recessive, bus 2 recessive, excluding inh1,inh2 output current bus 1 recessive, bus 2 dominant, excluding inh1,inh2 output current bus 1 dominant, bus 2 recessive, excluding inh1,inh2 output current bus 1 dominant, bus 2 dominant, excluding inh1,inh2 output current i s(rec1,rec2) i s(rec1,dom2) i s(dom1,rec2) i s(dom1,dom2) ? ? ? ? 8.0 12.0 12.0 12.0 9.0 13.0 13.0 16.0 ma rxd1, rxd2 output pins (logic) low level output voltage i in ? 1.5 ma v ol 0.0 ? 0.9 v high level output voltage v en = 5.0 v, i out ? 250 ? a v en = 3.3 v, i out ? 250 ? a v oh 4.25 3.0 ? ? 5.25 3.5 v notes 6. device is functional. all features are oper ating. electrical parameters are not guaranteed.
analog integrated circuit device data ? freescale semiconductor 11 33663 electrical characteristics static electrical characteristics txd1, txd2 input pins (logic) low level input voltage v il ? ? 0.8 v high level input voltage v ih 2.0 ? ? v input threshold voltage hysteresis v inhyst 100 300 600 mv pull-up current source v en = 5.0 v, 1.0 v < v txd < 3.5 v i pu - 60 - 35 - 20 ? a en1, en2 input pins (logic) low level input voltage v il ? ? 0.8 v high level input voltage v ih 2.0 ? ? v input voltage threshold hysteresis v inhyst 100 400 600 mv pull-down resistor r pd 100 230 350 kohm lin physical layer - transceiver lin (lin1, lin2) (7) operating voltage range (8) v bat 8.0 ? 18 v supply voltage range v sup 7.0 ? 18 v voltage range (within which t he device is not destroyed) v sup_non_op -0.3 ? 40 v current limitation for driver dominant state driver on, v bus = 18 v i bus_lim 40 90 200 ma input leakage current at the receiver driver off; v bus = 0 v; v bat = 12 v i bus_pas_dom -1.0 ? ? ma leakage output current to gnd driver off; 8.0 v ?? v bat ? 18 v; 8.0 v ?? v bus ? 18 v; v bus ? v bat ; ? v bus ?? v sup i bus_pas_rec ? ? 20 a control unit disconnected from ground (9) gnd device = v sup ; v bat = 12 v; 0 < v bus < 18 v i bus_no_gnd -1.0 ? 1.0 ma v bat disconnected; v sup_device = gnd; 0 v < v bus < 18 v (10) i busno_bat ? ? 10 a receiver dominant state (11) v busdom ? ? 0.4 v sup receiver recessive state (12) v busrec 0.6 ? ? v sup notes 7. parameters guaranteed for 7.0 v ?? v sup ? 18 v. 8. voltage range at the battery level, including the reverse battery diode. 9. loss of local ground must not affect communication in the residual network. 10. node has to sustain the current that can flow under this c ondition. the bus must remain operational under this condition. 11. lin threshold for a dominant state. 12. lin threshold for a recessive state. table 5. static elec trical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 12 freescale semiconductor 33663 electrical characteristics static electrical characteristics receiver threshold center (v th_dom + v th_rec )/2 v bus_cnt 0.475 0.5 0.525 v sup receiver threshold hysteresis (v th_rec - v th_dom ) v hys ? ? 0.175 v sup lin dominant level with 500 ??? 680 ? and 1.0 k ? load on the lin bus v lindom_level ? ? 0.3 v sup v bat _shift v shift_bat 0.0 ? 11.5% v bat gnd_shift v shift_gnd 0.0 ? 11.5% v bat lin wake-up threshold from sleep mode v buswu ? 4.3 5.3 v lin pull-up resistor to v sup r slave 20 30 60 k ? lin internal capacitor (13) c lin ? ? 30 pf over-temperature shutdown (14) t linsd 150 160 200 c over-temperature shutdown hysteresis t linsd_hys ? 20 ? c inh1, inh2 output pins driver on resistance (normal mode) i inh = 50 ma inh on ? ? 50 ? current load capability from 7.0 v < v sup < 18 v i inh_load ? ? 30 ma leakage current (sleep mode) 0 < v inh < v sup i leak -5.0 ? 5.0 ? a over-temperature shutdown (15) t inhsd 150 160 200 c over-temperature shutdown hysteresis t inhsd_hys ? 20 ? c notes 13. this parameter is guaranteed by process monitoring but not production tested. 14. when an over-temperature shutdown occurs, the lin transmitter and receiver are in recessive state and inh switched off. this parameter is tested with a test mode on ate and characterized at laboratory. 15. when an over-temperature shutdown occurs, the inh1, inh2 high side are switched off and the lin transmitter and receiver are in recessive state. this parameter is tested with a test mode on ate and characterized at laboratory. table 5. static elec trical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 13 33663 electrical characteristics static electrical characteristics wake1, wake2 input pins high to low detection threshold (5.5 v < v sup < 7 v) v wuhl1 2.0 ? 3.9 v low to high detection threshold (5.5 v < v sup < 7 v) v wulh1 2.4 ? 4.3 v hysteresis (5.5 v < v sup < 7 v) v wuhys1 0.2 ? 0.8 v high to low detection threshold (7 v ? v sup < 27 v) v wuhl2 2.4 ? 3.9 v low to high detection threshold (7 v ? v sup < 27 v) v wulh2 2.9 ? 4.3 v hysteresis (7 v ? v sup < 27 v) v wuhys2 0.2 ? 0.8 v wake-up input current (v wake < 27 v) i wu ? ? 5.0 a table 5. static elec trical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 14 freescale semiconductor 33663 electrical characteristics dynamic electrical characteristic dynamic electrical characteristic table 6. dynamic electri cal characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit lin1, lin2 physical layer drivers characteristics for normal slew rate - 20.0 kbit/sec according to lin physical layer specification (16) (17) 33663l and 33663s device duty cycle 1: th rec(max) = 0.744 * v sup ; th dom(max) = 0.581 * v sup d1 = t bus_rec(min) /(2 x t bit ), t bit = 50 s, 7.0 v ?? v sup ??? 18 v d1 0.396 ? ? duty cycle 2: th rec(min) = 0.422 * v sup ; th dom(min) = 0.284 * v sup d2 = t bus_rec(max) /(2 x t bit ), t bit = 50 s, 7.6 v ?? v sup ??? 18 v d2 ? ? 0.581 lin1, lin2 physical layer drivers characteristics for slow slew rate - 10.4 kbit/sec according to lin physical layer specification (16) (18) 33663j device duty cycle 3: th rec(max) = 0.778 * v sup ; th dom(max) = 0.616 * v sup d3 = t bus_rec(min) /(2 x t bit ), t bit = 96 s, 7.0 v ?? v sup ??? 18 v d3 0.417 ? ? duty cycle 4: th rec(min) = 0.389 * v sup ; th dom(min) = 0.251 * v sup d4 = t bus_rec(max) /(2 x t bit ), t bit = 96 s, 7.6 v ?? v sup ??? 18 v d4 ? ? 0.590 lin1, lin2 physical layer - drivers characteristics for fast slew rate fast bit rate (programming mode) br fast ? ? 100 kbit/s lin1, lin2 physical layer - transmitter c haracteristics for normal slew rate - 20.0 kbit/sec (19) 33663s device symmetry of transmitter delay (20) t tran_sym = max (t tran_sym60% , t tran_sym40% ) t tran_sym60% = | t tran_pdf60% - t tran_pdr60% | t tran_sym40% = | t tran_pdf40% - t tran_pdr40% | t tran_sym -7.25 ? 7.25 ? s notes 16. bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? ? , 10 nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 8 . 17. see figure 9 18. see figure 10 19. v sup from 7.0 to 18 v, bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 8 . 20. see figure 11
analog integrated circuit device data ? freescale semiconductor 15 33663 electrical characteristics dynamic electrical characteristic lin1, lin2 physical layer - receivers characteristics according lin2.1 (21) 33663l and 33663j and 33663s propagation delay and symmetry (22) propagation delay of receiver, t rec_pd = max (t rec_pdr , t rec_pdf ) symmetry of receiver propagation delay, t rec_pdf - t rec_pdr t rec_pd t rec_sym ? - 2.0 ? ? 6.0 2.0 ? s lin1, lin2 physical layer: receiver characteristics with tighten limits (21) 33663s device propagation delay and symmetry (22) propagation delay of receiver, t rec_pd = max (t rec_pdr , t rec_pdf ) symmetry of receiver propagation delay, t rec_pdf - t rec_pdr t rec_pd_s t rec_sym_s ? - 1.3 ? ? 5.0 1.3 ? s lin1, lin2 physical layer: receiver characteristics - lin slope 1v/ns (21) 33663s device propagation delay and symmetry (23) propagation delay of receiver, t rec_pd _fast = max (t rec_pdr_fast , t rec_pdf_fast ) symmetry of receiver propagation delay, t rec_pdf_fast - t rec_pdr_fast t rec_pd_fast t rec_sym_fast ? - 1.3 ? ? 6.0 1.3 ? s sleep mode and wake-up timings sleep mode delay time (24) after en high to low to inh high to low with 100a load on inh t sd 50 ? 91 s wake-up timings bus wake-up deglitcher (sleep mode) (25) t wuf 40 70 100 ? s en wake-up deglitcher (26) en high to inh low to high t lwue ? ? 15 ? s wake-up deglitcher (27) wake state change to inh low to high t wf 10 48 70 ? s notes 21. v sup from 7.0 to 18 v, bus load r bus and c bus 1.0 nf / 1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. see figure 8 . 22. see figure 12 23. see figure 13 24. see figures 22 and 23 25. see figures 15 and 17 26. see figures 14 , 18 , 22 , and 23 27. see figures 16 , 22 , and 23 table 6. dynamic elec trical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 16 freescale semiconductor 33663 electrical characteristics timing diagrams timing diagrams figure 8. test circui t for timing measurements txd timing txd permanent dominant state delay (28) t txddom 3.75 5.0 6.25 ms first dominant bit validation first dominant bit validation del ay when device in normal mode (29) t first_dom ? 50 80 ms fast baud rate timing en low pulse duration to enter in fast baud rate using toggle function (30) en high to low and low to high t 1 ? ? 45 ? s txd low pulse duration to enter in fast baud rate using toggle function (30) t 2 12.5 ? ? s delay between en falling edge and txd falling edge to enter in fast baud rate using toggle function (30) t 3 12.5 ? ? s delay between txd rising edge and en rising edge to enter in fast baud rate using toggle function (30) t 4 12.5 ? ? s rxd low level duration after en rising edge to validate the fast baud rate entrance (30) t 5 1.875 6.25 s notes 28. the lin is in recessive state and the receiver is still active 29. see figures 14 , 15 , 16 , and 21 30. see figures 19 and 20 table 6. dynamic elec trical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit lin gnd c 0 r 0 v sup vsup note r 0 and c 0 : 1.0 k ? /1.0 nf, 660 ? /6.8 nf, and 500 ? /10 nf. txd rxd
analog integrated circuit device data ? freescale semiconductor 17 33663 electrical characteristics timing diagrams figure 9. lin1, lin2 ti ming measurements for normal baud rate (33663l, 33663s) figure 10. lin1, lin2 timing meas urements for slow baud rate (33663j) txd lin rxd tbit tbit t bus_dom (max) t bus_rec (min) t rec_pdf(1) 74.4% v sup 42.2% v sup 58.1% v sup 28.4% v sup t bus_rec (max) v lin_rec t bus_dom (min) rxd output of receiving node 1 output of receiving node 2 th rec(max) th dom(max) th rec(min) th dom(min) thresholds of receiving node 1 thresholds of receiving node 2 t rec_pdr(1) t rec_pdf(2) t rec_pdr(2) txd lin rxd tbit tbit t bus_dom (max) t bus_rec (min) t rec_pdf(1) 77.8% v sup 38.9% v sup 61.6% v sup 25.1% v sup t bus_rec (max) v lin_rec t bus_dom (min) rxd output of receiving node 1 output of receiving node 2 th rec(max) th dom(max) th rec(min) th dom(min) thresholds of receiving node 1 thresholds of receiving node 2 t rec_pdr(1) t rec_pdf(2) t rec_pdr(2)
analog integrated circuit device data ? 18 freescale semiconductor 33663 electrical characteristics timing diagrams figure 11. lin1, lin2 transmitter timing for 33663s figure 12. lin1, lin2 receiver timing figure 13. lin1, lin2 rece iver timing lin slope 1.0 v/ns v busrec v busdom v sup lin bus signal t tran_pdf60% txd v lin_rec 40% v sup 60% v sup t tran_pdf40% t tran_pdr40% t tran_pdr60% v busrec v busdom v sup lin bus signal t rec_pdr t rec_pdf rxd v lin_rec 40% v sup 60% v sup v busrec v busdom v sup lin bus signal t rec_pdr_fast t rec_pdf_fast rxd v lin_rec 40% v sup 60% v sup 1v/ns
analog integrated circuit device data ? freescale semiconductor 19 33663 electrical characteristics functional diagrams functional diagrams figure 14. lin module 1 en1 pin wake-up with txd1 high & lin module 2 in normal mode figure 15. lin module 1 in normal mode & lin module 2 lin2 wake-up with txd2 low inh1 en1 lin1 t lwue rxd1 (high z) txd1 (high or low) normal mode wake1 normal mode en2 inh2 lin2 rxd2 wake2 txd2 v buswu t wuf rxd2 (high z) awake mode txd2 (high or low) wake2 lin2 inh2 en2 normal mode en1 inh1 lin1 rxd1 wake1 txd1 t first_dom normal mode
analog integrated circuit device data ? 20 freescale semiconductor 33663 electrical characteristics functional diagrams figure 16. lin module 1 wake1 pin wake-up with txd1 low & lin module 2 wake2 pin wake-up with txd2 high wake1 t wf txd1 (high or low) inh1 en1 lin1 rxd1 rxd2 (high z) awake mode wake after deglitcher t wf rxd2 (high z) awake mode wake after deglitcher wake2 inh2 en2 txd2 (high or low) lin2 t first_dom t first_dom normal mode normal mode
analog integrated circuit device data ? freescale semiconductor 21 33663 electrical characteristics functional diagrams figure 17. bus wake-up with lin bus in dominant during the preparation to sleep mode (same sequence for lin1 & lin2) figure 18. en1, en2 pi n deglitcher figure 19. fast baud rate selection (toggle function) for lin1 or lin2 inh en lin t>t wuf rxd (high z) txd wake t sd sleep mode preparation to sleep mode device in communication mode awake normal mode mode no wake-up no communication available wake & lin wake-up events not taken into no communication available account wake & lin wake-up events allowed en pin en internal signal t lwue t lwue en internal signal en pin t < t lwu e en internal signal en pin t < t lwu e 5v 5v txd en t 1 (45 ? s) fast baud rate entrance lin rxd t 5 fast baud rate validation t 2 (12.5 ? s) t 4 (12.5 ? s) t 3 (12.5 ? s)
analog integrated circuit device data ? 22 freescale semiconductor 33663 electrical characteristics functional diagrams figure 20. fast baud rate mode exit (back to normal or slow slew rate) for lin1 or lin2 figure 21. power up and down sequences txd en t 1 (45 ? s) exit fast baud rate t 2 (12.5 ? s) t 4 (12.5 ? s) t 3 (12.5 ? s) lin rxd rxd stays high for normal or slow mode validation inh1 en1 lin1 rxd1 txd1 inh1 en1 lin1 rxd1 txd1 vsup por (3.5-5.3 v) vsup v uvl awake mode lin1 in normal mode (high z) (high z) (high or low) 160 s * (high or low) (high or low) por (3.5-5.3 v) en2 lin2 rxd2 txd2 awake mode lin2 in normal mode (high z) *: this parameter is guaranteed by design (high or low) inh2 inh2 en2 lin2 rxd2 txd2 (high z) (high or low) (high or low)
analog integrated circuit device data ? freescale semiconductor 23 33663 electrical characteristics functional diagrams figure 22. sleep mode sequence for lin1 or lin2 txd en t sd sleep preparation to sleep mode device in inh wake lin rxd (high z) communication mode no communication allowed lin & wake wake up events not taken into account t lwue wake after deglitcher t wf mode
analog integrated circuit device data ? 24 freescale semiconductor 33663 electrical characteristics functional diagrams figure 23. examples of sleep mode sequences for lin1 or lin2 txd en t < t sd awake mode preparation to device in inh wake sleep mode t = t wf lin rxd the device does not enter in sleep mode (high z) (case 1) txd en awake mode device in inh wake t ?? t wf lin rxd the device does not enter in sleep mode (high z) (case 2) communication mode communication mode sleep mode (t < t sd ) preparation to t lwue wake after deglitcher (case 1) t lwue wake after deglitcher (case 2) txd en awake mode device in inh wake t ?? t wf lin rxd (high z) (case 3) communication mode sleep mode preparation to t lwue wake after deglitcher (case 3) no communication allowed no communication allowed t ?? t sd sleep mode no communication allowed
analog integrated circuit device data ? freescale semiconductor 25 33663 functional description introduction functional description introduction the 33663l and 33663j are both a physical layer compo nent dedicated to automotive lin sub-bus applications. the 33663l features include a 20 kbps baud rate and the 33663j a 10 kbps baud rate. both integrate fast baud rate for test and programming modes, excellent esd robustness, immunity ag ainst disturbance, and radiated emission performance. they have safe behavior, in case of a lin bus short-to-g round, or a lin bus leakage during low power mode. digital inputs are 5.0 and 3.3 v compatible without any ex ternal required components. the inh1 and inh2 outputs may be used to control an external voltage regulator, or to dr ive a lin bus pull-up resistor. functional pin description power supply pin (vsup) the vsup supply pin is the power supply pin for the 33663l or 33663j. in an application, the pin is connected to a battery through a serial diode, for reve rse battery protection. the dc o perating voltage is from 7.0 to 18 v. this pin sustains standard automotive condition, such as 40 v during load dump. to avoid a false bus message, an under-voltage on vsup disables the transmission path (from txd to lin) when v sup falls below 6.7 v. supply current in the sleep mode is typically 6.0 ? a for one lin module. ground pin (gnd) in case of a ground disconnection at the module level, t he 33663l and 33663j do not have sign ificant current consumption on the lin bus pin when in the recessive state. lin bus pin (lin1, lin2) the lin1 and lin2 pins repres ent the single-wire bus transmitter and receiver. it is suited for automotiv e bus systems, and is compliant to the lin bus specificat ion 1.3, 2.0, 2.1, and saej2602-2. the lin interface is only active during normal mode. transmitter characteristics the lin driver is a low side mosfet with internal over-current thermal shutdown. an internal pull-up resistor with a serial diode structure is integrated, so no external pull-up componen ts are required for the application in a slave node. an additiona l pull-up resistor of 1.0 k ? must be added when the interfac e is used in the master node. the lin pin exhibits no reverse cu rrent from the lin bus line to v sup , even in the event of a gnd shift or v sup disconnection. the 33663 is tested according to the application conditions (i.e . in normal mode and recessive state during communication). the transmitter has a 20 kbps baud rate (normal baud rate) for the 33663l and 33663s devices, or 10 kbps baud rate (slow baud rate) for the 33663j device. txd rxd 35a lin driver lin vsup en_sleep inh_on slope control receiver ? 725 k 30 k ? inh lin undervoltage lin overtemperature txd dominant lin wake up en x 1 inh overtemperature inh switched off & lin transmitter and receiver disabled or
analog integrated circuit device data ? 26 freescale semiconductor 33663 functional description functional pin description as soon as the device enters normal mode, the lin transmitte r will be able to send the first dominant bit only after the t first_dom delay. t first_dom delay has no impact on the receiver. the receiver will be enabled as soon as the device enters normal mode. receiver characteristics the receiver thresholds are ratiom etric with the device supply pin. if the v sup voltage goes below the v sup under-voltage threshold ( v uvl , v uvh ), the bus lin1 and bus lin2 enter into a recessive state even if communication is sent to txd1 or txd2. for the lin module 1, in case of lin1 th ermal shutdown, the transceiver and receiver are in recessive and inh1 turned off. when the temperature is below the t linsd , inh1 and lin1 will be automatically enabled. the same behavior is valid for lin module 2. for each lin module, the fast baud rate selection is reported by the rxd pin. fast baud rate is activated by the toggle function (see figure 19 ). at the end of the toggle fu nction, just after en rising edg e, rxd pin is kept low for t 5 to flag the fast baud rate entry (see figure 19 ). to exit the fast baud rate and return in normal or slow baud rate, a toggle function is needed. at the end the toggle function, rxd pin stays high to signal fast baud rate exit (see figure 20 ). the device enters into fast baud rate at room and hot temperature. data input pins (txd1, txd2) the txd1 and txd2 inputs pins are the mcu interface to contro l the state of the lin1 and lin2 outputs. when txd1 (txd2) is low (dominant), lin1 (lin2) output is low; when txd1 (txd 2) is high (recessive), the lin1 (lin2) output transistor is turned off. txd1/txd2 pins thresholds are 3.3 v and 5.0 v compatible. these pins have an internal pull-up current source to fo rce the recessive state if the input pins are left floating. if txd1 (txd2) stays low (dominant sate) more than 5.0 ms (typical value), the lin1 (lin2) transmitter of lin module goes automatically into recessive state. data output pins (rxd1, rxd2) each lin modules integrate the same rxd output structure and functionality. bo th pins are independent. the following description is the same for both. rxd output pin is the mcu inte rface, which reports the stat e of the lin bus voltage. in normal or slow baud rate, lin high (recessive) is reported by a high voltage on rxd; lin low (domin ant) is reported by a low voltage on rxd. the rxd output st ructure is a tristate output buffer. figure 24. rxd interface the rxd output pins are the receiver outp ut of the lin interface. the low level is fixed. the high level is dependent on en voltage. if en is set at 3.3 v, rxd v oh is 3.3 v. if en is set at 5.0 v, rxd v oh is 5.0 v. the rxd1 and rxd2 v oh level can be defined independently. in sleep mode, rxd are high-impedance. when a wake-up event is recognized from the wake pin or from the lin bus pin, rxd is pulled low to report the wake-up event. an external pull-up resistor may be needed. rxd en 200 k ? x 1 en_rxd lin vsup slope cont rol recei ver ? 30 k lin_rxd
analog integrated circuit device data ? freescale semiconductor 27 33663 functional description functional pin description enable input pins (en1, en2) en1 (en2) input pin controls the operatio n mode of the interface. if en1 (en2) = 1, the interface is in normal mode, txd1 (txd2) to lin1 (lin2) after t firs_dom delay and lin1 (lin2) to rxd1 (rxd2) paths are both active. en1 (en2) pin thresholds are 3.3 v and 5.0 v compatible. rxd1 (rxd2) v oh level follows en1 (en2) pin high level. one lin module enters the sleep mode by setting en1 (en2) low for a delay higher than t sd (70 s typ. value) and if the wake1 (wake2) pin state doesn?t change during this delay . (see figure 22 ). both lin modules enter sleep mode if en1 & en2 low. a combination of the logic levels on en1 (en2) and txd1 (txd2) pins allows the device to enter in fast baud rate mode of operation (see figure 19 ). inhibit output pins (inh1, inh2) the inh1 (inh2) output pin is c onnected to an internal high side power mosfet . the pin has two possible main functions. it can be used to control an external switchable voltage regulator having an inhibit input. it can also be used to drive the lin b us external resistor in the master node application, thanks to its high dr ive capability. this is illustrated in figure 26 . in sleep mode, inh1 (inh2) is turned off. if a voltage regulato r inhibit input is connected to inh1 (inh2), the regulator will be disabled. if the master node pull-up resi stor is connected to inh1 (inh2), the pull-up resistor will be unpowered and left floating. in case of a inh1 (inh2) thermal shutdown, the high side is turned off and the lin1 (lin2) transmitter and receiver are in recessive state. an external 10 to 100 pf capacitor on inh1 (inh2) pin is advised in order to improve emc performances. wake input pins (wake1, wake2) the wake1 (wake2) pin is a high-voltage input used to wake-up the de vice from the sleep mode. wake1 (wake2) is usually connected to an external switch in the application. the wake1 (wake2) pin has a special desi gn structure and allows wa ke-up from both high to low or low to high transitions. when entering into sleep mode, the corresponded lin module monitors the st ate of its wake pin and stores it as a reference state. the opposite stat e of this reference state will be the wake-up even t used by the lin module to enter again int o normal mode. if the wake1 (wake2) pin state changes during the sleep mode delay time (t sd ) or before en1 (en2) goes low with a deglitcher lower than t wf , the lin module will not enter in sleep mode, but will go into awake mode (see figure 23 ). an internal filter is implemented to avoid false wake-up event due to parasitic pulses (see figure 16 ). wake1 (wake2) pin input structure exhibits a high-impedance, with extremely low input current when voltage at this pin is below 27 v. two serial resistors should be inserted in order to limit the input current mainly during transient pulses and esd. the total recommended resistor value is 33 k ? . an external 10 to 100 nf capacitor is advised for better emc and esd performances. important the wake1 (wake2) pin should not be left open. if the wake-up function is not used, wake1 (wake2) should be connected to ground to avoid a false wake-up.
analog integrated circuit device data ? 28 freescale semiconductor 33663 functional device operation operational modes functional device operation operational modes as described by the following, the 33663l, 33663j, and 33663s have two operational modes, normal and sleep. in addition, there are two transitional modes: awake mode which allows the de vice to go into normal mode, and preparation to sleep mode which allows the device to go into sleep mode. normal or slow baud rate in the normal mode, the lin bus can transmit and receive information. the 33663l and 33663s (20 kbps) have a slew rate and timing compatible with normal baud rate and lin protocol specification 1.3, 2. 0, 2.1, and 2.2. the 33663j (10 kbps) has a slew rate and timing compatible with low baud rate. from normal mode, the three devices can enter into fast baud rate (toggle function). fast baud rate in fast baud rate, the slew rate is aro und 10 times faster than the normal baud rate. this allows very fast data transmission (> 100 kbps) -- for example, electronic control unit (ecu) tests and mi crocontroller program download. the bus pull-up resistor might be adjusted to ensure a correct rc time constant in line with the high baud rate used. the following sequence is applicable to both lin modules independently. fast baud rate is entered via a special seque nce (called toggle function) as follows: 1. en1 pin set low while txd1 is high 2. txd1 stays high for 12.5 s min 3. txd1 set low for 12.5 s min 4. txd1 pulled high for 12.5 s min 5. en1 pin set low to high while txd1 still high the lin module enters into the fast baud rate if the delay between step 1 to step 5 is 45 s maximum. the toggle function is described in figures 19 . once in fast baud rate, the same toggle function just described previously is used to bring the lin module 1 back into normal baud rate. fast baud rate selection is reported to t he mcu by the rxd1 pin. once the lin modul e 1 enters in this fast baud rate, the rxd1 pin goes at low level for t 5 . when lin module 1 returns to normal baud rate with the same toggle function, the rxd1 pin stays high. both sequences are illustrated in figures 19 and 20 . preparation to sleep mode the following sequence is applicable to both lin modules simulta neously or separately. here it is detailed with the lin module 1. to enter the preparation to sleep mode, en1 must be low for a delay higher than t lwue . ? if the wake1 pin state doesn?t change during t sd and t lwue , then the lin module 1 goes in sleep mode. ? if the wake1 pin state changes during t sd and if t wf is reached after end of t sd , then the lin module 1 goes into sleep mode after the end of t sd timing. ? if the wake1 pin stat e changes during t sd and t wf delay has been reached before end of t sd , then the lin module 1 goes into awake mode. ? if the wake1 pin state changes before t sd and the delay t wf ends during t sd , then the lin module 1 goes in awake mode. ? if en1 goes high for a delay higher than t lwue , the lin module 1 returns in normal mode. sleep mode the following sleep mode paragraph is applicable to both lin modules simultaneously or se parately. lin module 1 is an example. to enter into sleep mode, en1 must be low for a delay longer than t sd and the wake1 pin must stay in the same state (high or low) during this delay. the lin module 1 conditions to not enter sleep mode, but enter awake mode are detailed in the preparation into sleep mode chapter. see figure 23 .
analog integrated circuit device data ? freescale semiconductor 29 33663 functional device operation operational modes in sleep mode, the transmission path is disabled and the li n module 1 is in low power mode. supply current from v sup is very low. wake-up can occur from lin1 bus activity, from the en1 pin and from the w ake1 input pin. if du ring the preparation to sleep mode delay (t sd ), the lin1 bus goes low due to lin1 network comm unication, the lin module 1 still enters sleep mode. the lin module 1 can be awakened by a recessive to dominant start, followed by a dominant to recessive state after t > t wuf . after a wake-up event, the lin module 1 enters into awak e mode. in sleep mode, the lin module 1 internal 725 kohm pull- up resistor is connected and the 30 kohm is disconnected. device power-up (awake transitional mode) at power-up (v sup rises from zero), when v sup is above the power-on reset voltage, bo th lin modules automatically switch after a 160 s delay time to the awake transitional mode. both inh pi ns (inh1 and inh2) go to a high state and rxd1and rxd2 to a low state. see figure 21 . device wake-up events the 33663l, 33663j and 33663s can be awakened fr om sleep mode by three wake-up events: ? remote wake-up via lin1 and/or lin2 bus activity ? via the en1 and/or en2 pin ? toggling the wake1 and/or wake2 pin remote wake from lin1, lin2 bus (awake transitional mode) each lin transceiver is awakened by its lin dominant pul se longer than t wuf . dominant pulse means: a recessive to dominant transition, wait for t > t wuf , then a dominant to recessive tran sition. this is illustrated in figure 15 . once the wake-up is detected (during the dominant to recessive transition), the lin module wa ken up by its lin enters into awake mode, with its inh high and rxd pulled low. once in the awake mode, its en pin has to be set to 3.3 v or 5.0 v (depending on the system) to enter into normal mode. once in normal mode, the lin module has to wait t first_dom delay before transmitting the first dominant bit. wake-up from en1, en2 pins each lin module can be awakened by a low to high transition of its en pin. when en is switched from low to high and stays high for a delay higher than t lwue , the lin module is awakened and enters into normal mode. see figure 14 . once in normal mode, the lin module has to wait t first_dom delay before transmitting the first dominant bit. wake-up from wake1, wake2 pins (awake transitional mode) just before entering the sleep mode, the wake pin state of the concerned lin module is stored. a change in the level longer than the deglitcher time (70 s maximum) will generate a wake-up, and the lin module enters into the awake transitional mode, with its inh high and rxd pulled low. see figure 16 . the lin module goes into normal mode when its en is switched from low to high and stays high for a delay higher than t lwue . once in normal mode, the lin module has to wait t first_dom delay before transmitting the first dominant bit.
analog integrated circuit device data ? 30 freescale semiconductor 33663 functional device operation operational modes fail-safe features tables 7 describes the 33663 protections. table 7. fail safe features block fault functiona l mode condition fallout recovery condition recovery functionality mode power supply power on reset (por) all modes v sup < 3.5 v (min) then power up no internal supplies condition gone device goes in awake mode whatever the previous device mode inh1 inh2 inh1 and/or inh2 thermal shutdown. each lin module has its own inh thermal shutdown. for the failed lin module: normal, awake & preparation to sleep modes temperature > 160 c (typ) inh high side of the failed lin module turned off and its lin transmitter and receiver in recessive state condition gone lin module returns in same functional mode lin1 lin2 v sup under- voltage normal v sup < v uvl both lin transmitters in recessive state condition gone device returns in same functional mode txd1 and/or txd2 pins permanent dominant txd pin low for more than 5.0 ms (typ) lin transmitter of the failed lin module in recessive state condition gone lin module returns in same functional mode lin1 and/or lin2 thermal shutdown. each lin module has its own lin thermal shutdown. normal mode temperature > 160 c (typ) lin transmitter and receiver of the failed lin module in recessive state and its inh high side turned off condition gone lin module returns in same functional mode
analog integrated circuit device data ? freescale semiconductor 31 33663 functional device operation operational modes figure 25. operational and transitional modes state table 7. explanation of operat ional and transitional modes state diagram (each transceiver) operational/ transitional lin1, lin2 inh1 inh2 en1 en2 txd1, txd2 rxd1, rxd2 sleep mode recessive state, driver off with ? 725 k ? pull-up. off (low) low x high-impedance. high if external pull-up to v dd. awake recessive state, driver off. ? 725 k ? pull-up active. on (high) low x low. if external pull-up, high-to-low transition reports wake-up. preparation to sleep mode recessive state, driver off with ? 725 k ? pull-up on (high) low x high-impedance. high if external pull-up to v dd. normal mode driver active. 30 k ? pull-up active. ? normal baud rate for 33662l and 33662s slow baud rate for 33662j fast baud rate (> 100 kbps) for 33662l, 33662s & 33662j on (high) high low to drive lin bus in dominant high to drive lin bus in recessive. report lin bus state: ? ? low lin bus dominant ? ? high lin bus recessive x = don?t care. power-up awake sleep preparation to sleep lin1 normal baud rate or slow baud rate fast baud rate (10x) en1 high to low for t >t lwue en1 low to high for t> t lwue en1 low to high for t>t lwue toggle function (4) toggle function (4) en1 high to low for t >t lwue en1 low to high for t >t lwue lin module 1 sleep preparation to sleep lin2 normal baud rate or slow baud rate fast baud rate (10x) en2 low to high for t > t lwue en2 high to low for t >t lwue toggle function (4) toggle function (4) en2 high to low for t >t lwue en2 low to high for t >t lwue en2 low to high for t >t lwue lin module 2 awake lin1 bus dominant pulse for t >t wuf (2) or wake1 pin state changes for t >t wf (3) internal wake1 (1) state changes during t sd lin2 bus dominant pulse for t>t wuf (2) or wake2 pin state changes for t >t wf (3) internal wake2 (1) state changes during t sd vsup > vpor internal wake1 (1) state doesn?t change during t sd internal wake2 (1) state doesn?t change during t sd (1) :internal wake is the wake signal filtered by t wf (wake deglitcher) (2 ) :see figures 15 and 18 (3 ) :see figures 14 and 17 (4 ) :the toogle function is guaranteed at ambiant and hot temperature
analog integrated circuit device data ? 32 freescale semiconductor 33663 functional device operation operational modes compatibility with lin1.3 following the consortium lin specification package, revision 2. 1, november 24, 2006, chapter 1.1.7.1 compatibility with lin1.3 page 15: the lin 2.1 physical layer and is backward compatible with the lin 1.3 physical layer, but not the other way around. the lin 2.1 physical layer sets harder requirement s, i.e. a node using the lin 2.1 physical layer can operate in a lin 1.3 cluster.
analog integrated circuit device data ? freescale semiconductor 33 33663 typical application operational modes typical application the 33663 can be configured for several applic ations. the figure below shows lin2 as a slave node and lin1 as a master node application. an additional pull-up resistor of 1.0 k ? in series with a diode must be added when the device is used in the master node. figure 26. 33663 typical application * v dd rxd1 txd1 i/o mcu v dd regulator 12v 5v or 3.3v d1 c1 47f c2 100nf vbat lin bus1 i/o_2 rxd2 txd2 c3 100nf txd1 rxd1 en1 inh1 lin1 gnd inh2 lin2 lin bus2 r6 1k d2 wake1 vsup wake2 r1 18k * v dd txd2 rxd2 en2 r2 18k c4 100nf r4 18k r5 18k lin module 2 (lin 2) 33663 r6 2.2k r3 2.2k *: optional 2.2k if implemented lin module 1 (lin 1)
analog integrated circuit device data ? 34 freescale semiconductor 33663 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit ww w.freescale.com and do a keyword search on the 98a. dimensions shown are provided for reference only. ef suffix 14-pin 98asb42565b revision j
analog integrated circuit device data ? freescale semiconductor 35 33663 packaging package dimensions ef suffix 14-pin 98asb42565b revision j
analog integrated circuit device data ? 36 freescale semiconductor 33663 revision history revision history revision date description of changes 1.0 7/2012 ? initial release.
document number: MC33663 rev. 1.0 7/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. ? airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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